Electronic circuit



March 1954 A. H. DICKINSON ELECTRONIC CIRCUIT l5 Sheets-Sheet 1 OriginalFiled June 18, 1949 INVENTOR.

ARTHUR H.D|CK|NSON ATTORNEY March 16, 1954 A. H. DICKINSON ELECTRONICCIRCUIT Original Filed June 18, 1949 15 Sheets-Sheet 2 ARTHUR H.DICKINSON ATTORNEY March 1954 A. H. DICKINSON ELECTRONIC CIRCUIT l5Sheets-Sheet 3 Original Filed June l8, 1949 4 INVENTOR ARTHUR H.DICKINSON ATTORNEY March 1954 A. H. DICKINSON ELECTRONIC CIRCUIT l5Sheets-Sheet 4 Original Filed June 18, 1949 m m E H.DICKINSON AT TORNEYMamh 1954 A. H. DICKINSON ELECTRONIC CIRCUIT 15 Sheets-Sheet 5 OriginalFiled June 18, 1949 ZNVENTOR.

March 16, 1954 Original Filed June 18, 1949 A. H. DICKINSON ELECTRONICCIRCUIT 15 Sheets-Sheet 6 IN VEN TOR. 'ARTHUR H. DICKINSON WQW ATTORNEYMarch 1954 A. H. DICKINISON ELECTRONIC CIRCUIT Original Filed June 18,1949 15 Sheets-Sheet 7 INVENTOR.

ARTHUR H. DICKINSON ATTORNEY March 1954 A. H. DICKINSON ELECTRONICCIRCUIT Original Filed June 18, 1949 b ammo/1 Mpl/ r0 Mp7 To Mpl/ 15Sheets-Sheet 9 mam; m rm warm um M,

INVENTOR. ARTHUR H. DICKINSON ATTORNEY March 16, 1954 Original FiledJune 18, 1949 A. H. DICKINSON ELECTRONIC CIRCUIT 15 Sheets-Sheet 10 INVEN TOR. ARTHUR H. DICKINSON ATTORNEY March 16, 1954 A. H. DICKINSONELECTRONIC CIRCUIT Original Filed June 18, 1949 TEA-0L 15 Sheets-Sheet ll INVENTOR. ARTHUR H.D|CKINSON ATTORNEY March 12 1954 A. H. DICKINSON2,672,553

ELECTRONIC CIRCUIT Original Filed June 18, 1949 15 Sheets-Sheet 15INVENTOR. ARTHUR H.DICK|NSON QMW )vwa,

ATTORNEY March 16, 1954 A. H. DICKINSON 2,672,553

ELECTRONIC CIRCUIT Q Original Filed June 18 1949 15 Sheets-Sheet l4INVENTOR. ARTHUR H. DICKINSON ATTORNEY March 1954 A. H. DICKINSON2,672,553

ELECTRONIC CIRCUIT Original Filed June 18, 1949 15 Sheets-Sheet l5 INVENTOR. ARTHUR H. DICKINSON v WEW ATTORNEY Patented Mar. 16, 1954 UNITEDSTATES PATENT OFFICE ELECTRONIC CIRCUIT Arthur H. Dickinson, Greenwich,Conn., assignor to International Business Machines Corporation, NewYork, N. Y., a corporation of New York Original application June 18,1949, Serial No. 99,959, now Patent No. 264,407, dated June 9, 1953.Divided and this application November 15, 1951, Serial No. 256,573

This invention relates to electronic circuitry and more particularly tonovel electronic circuitry within a multiplier wherein the product isobtained by over-and-over addition without employing column shift.

One of the principal considerations in multi plier design has been thespeed of the multiplying operation. To effect an increase in this speed,column shift is employed to decrease the number of cycles of operationrequired to solve a given problem. such is desirable in mechanicalmultipliers due to the inherent factors limiting their speed ofoperation. However, an electronic multiplier operates so fast that thenumber of cycles of operation necessary to solve a given problem ceasesto be a major consideration so far as its practical applications areconcerned. In such multipliers it is conventional to enter themultiplicand and multiplier into receiving devices which contain aseparate order for each of the digits.

Accordingly, a principal object of this invention is to provide animproved electronic multiplier which employs a single order multiplicandreceiving device to accommodate a multiplicand having a plurality oforders.

A further object is to provide an electronic multiplier having a novelmultiplicand receiving device wherein the value or" the multiplierdetermines the entry of pulses into the multiplicand receiving device.

Another object is to provide a novel single order multiplicand receivingdevice having a series of digit-representing push-button type switchesfor each order of the multiplicand, said switches corresponding to thedigit-representing elements of the receiving device and connected totransfer a response therefrom in accordance with the value of therespective digits of the multiplicand.

Another object is to provide a novel circuit arrangement to permit thesimultaneous entry of all digital values of the multiplicand into theresult register during one cycle of the multiplicand receiving device.

Another object is to provide a novel circuit arrangement wherein achange in the stable condition of one digit-representing element of themultiplier receiving device is utilized to prevent further entries intothe multiplicand receiving 6 Claims. (Cl. 250-27) device, the resultregister and the multiplier receiving device.

An ancillary object is to provide a circuit which is responsive topulses, when read out pulses are not being made into the multiplicandreceiving device, to effect a simultaneous switching of all thedigit-representing elements thereof to a preselected stable condition.

A still further object is to provide a novel circuit arrangementincluding a trigger switchable to one stable condition in response to apulse from one source so that it permits entries to be made into themultiplicand receiving device and switchable to its other stablecondition in response to a pulse from another source only when themultiplicand receiving device has completed a cycle of operation.

A still further object is to provide a novel circult arrangementpermitting the entry of a number of pulses equal to one less than thevalue of each digit, other than zero, of the multiplicand into eachcorresponding order of the result register when the multiplicandreceiving device is being sequentially operated and permitting only oneadditional entry to be made simultaneously into each such order of theresult register, said entries also being made prior to the switching ofthe digit-representing elements of the multiplicand receiving device totheir preselected condition of stability.

Generally, the multiplier comprises a source of pulses, multiplicand andmultiplier receiving devices and a result register inter-connected in anovel manner to perform the multiplication of two numbers representing amultiplicand and a multiplier, respectively. The multiplicand andmultiplier are entered into their respective receiving devices bydepressing the proper pushbutton switches thereof and their product isdisplayed by the result register. The novel multiplicand receivingdevice uses a single series of nine digit-representing elements toaccommodate a multiplicand having a plurality of digital orders.

The closing of a calculate switch conditions the entire multiplier tostart multiplication of the entered numbers in response to the source ofpulses. A multiplier interpreter circuit is provided to respond to themultiplier receiving device to effect the operation of a trigger whenthe multiplier receiving device has received a number of pulses equal tothe one-thousands complement of the particular multiplier used. When thestable condition of the trigger is switched it causes an electronic atecontrol circuit to be energized to permit read out pulses to be enteredinto the multiplicand receiving device to effect a sequential switchingof the digit-representing elementsithere'of.

When the multiplica'nd receiving device receives a number of entriesequal to the tens complement of the multiplicand digit of the lowestorder and the nines complement of each. higher order thereof anelectronic gate is opened to permit entries into the correspondingorder-of one :time.

"The gate c'ontrollingtrigger is again energized andth multiplicand isagain entered into the result register. Such is continued un'til thetriggercannot beenergized' again becauseof the vcorriplet'ioncf a cycleof operation by the' multiplier receiving deviceJThe multiplicand hasnow been 'enteredinto the result-register a numberof times. equal tothe-multiplier.

Otherobjects of the invention will be pointed .out' in th 'iollowingdescription and claims 1 and illustrated in'the accompanyingdrawings,which dis'close',by'way of example, the-principle of the invention andthe best mode, which has been contemplated, of applying that principle.In thedrawings:

Fig. I is a; blockdiagram illustrating one em- 4 bodiment of themultiplierof-theinvention.

,'"Fig: 2' is acircuitdiagramof a trigger circuit typical of thoseemployedby the invention.

Fig. 2a is a'diagrammatic' showing'of the trig- "ger' circuit of' Fig.2.

*Fig. Sshows the-relative 'arrangement'of subsequent figures to realizethe complete circuit diagram of the'multiplier.

prise a circuit'diagram oi the multiplier.

""Fig. 4 showstherelative' arrangement of subseiquent figures to-realizea timing chart represntative of the operation of the multiplier inperforming a. specified problem; and Figsra, ib, 4c,*4d, 4e,- if 4g;and4h taken together represent a timing chart showing th operationofa-multiplier when the solution of a specified problem is accomplished.

Various electronic circuits; each employing onetube, are "employed bythe invention." I When "'theelectrode potentals of the tubes are atcertain predetermined *valuesgthesetubes respond "to aninput pulse tomomentarily change their conductive state and usually to effect someother operation. When the electrode potentials are at certain othervalues thetubes will not respond --to-an inputpulse' Such circuits arereferred to circuits are referred to as gate J tubes. When such a tubewil'lnot respond to its usualinput herein as gates and the tubes mployedin the pulse it is-referred to as "de-conditionew and when itwillrespond-to that input it is referred to as -condition'e'd.

h A number of trigger circuits are employedhaving two tubes, "oneconductive and the other "non-conductive and vice versa to represent twostable conditions. These "two conditions are i referredgto herein-astheLeft and Right condition. "I3eft"'condition"means that" the left handtube of the trigger is conductive and that the righthand tube isnon-conductive. Right condition" means that the right-hand tube of thetrig- :ger is conductive and thatvthesleft-hand tube is non-conductive.

To facilitate the description the specification i is divided into anumber of designated parts.

Portions. of the multiplier which do not have a ''''designated parttherefor are described in connection' .with the designated part deemedmost :.-per'tinent.

"GENERAL DESCRIPTION czThegenera l scheme of the invention will now 'be"*explainedfzwitm reference to the block diagram of Fig. 1.

To effect 'niulti'plication the multiplicand is entered in the resultregister a number of times equal to the multiplier. The speed of theactual multiplication is determined by the frequency of tthe pulsesusedto 'efiect itwhich-pulses maybe of a fixedfrequency" or may occur atrandom.

"The pulses'used to effectoperat-ion are derived from an oscillator l0and a circuit-network 'li actuatedhytheoscillator Ill. The oscillatorHl' producestwo distinctseries ofpbsltiveand negativepulses.-*The'-pulses of one series 'are referred to as E- pulses and thepulses ofthe other series are referred toas F pulses." The positive Epulses "are 'one-hundred and eighty" degrees out of phase with thenegative E pulses and phase 'with'the negative F'pulses." Ac-"cordingly; the positive F pulses are one-hundredand-eighty'degrees'outof phase with the-negative F pulses'and in phase with the negativeE'pulses.

' The E pulses appear on a -'-lead l0E and'the" F pulses appear on'a'lead- IOF.

The F pulses are transferred over the lead IBF to actuate circuitnetwork l-l to' cause it toproduce two distinct *seriesor positiveandnegative pulses. i Thepulses'ofone series'are referredto as C pulsesand the pulses of-the other series are referred to as' D- pulses. Thepositive C pulses are -one-hundred-and-eighty- *degrees out'of phasewith the negative C pulses and in phase with the negativeD'pulses."Accordingly the positive- D- pulses are-'one-hundred-and-eighty degreesout of phase-with the negative D pulses and in-phase with the negative Cpulsess @119 C pulse and one D pulse occur foi each sixteenth negative Fpulse." The C pulses appear- 01i a lead i'lC'and the-Dspulses appear ona lead HD.

- The multiplicand receiving device Mcs'comprises a single orderreceiving'devicesequentially operable to produce an output'foreachorder'of the multiplicand' in response to the condition of theassociated push-button switchesprovided-to accommodate a" multiplicandof three orders. I The multiplierreceiving device Mp comprises aseparate. order for-each order of the multiplier, there being'shown:the' orders MpU. MpT; and

. MpI-I corresponding -'respectivelyto the: units,

tens, and hundredsidigit of thenm'ultiplier. #The particularcorresponding multiplier-digit iszen- 'tered in-the correct. :order ofthe :multi-pl-ier by depressing the correct push-button switch-:associated therewith.

.The result register RR comprises six orders labeled RRU, RRT,RRflpRRTh} RRT-Th, and RRHTh to, designate. the units, tens, hundreds,thousands; ten-thousands, and hundred-thousands orders. respectively. Epulses are continuously transferred over the leads NE and". I 2 to theunits or-def .RRU 'a'nd' over the leal'd's'. I'DE, l2 and 13' to thetensrder RRT. The six'orders of the result register are provided toaccommodate the product of a three-digit multiplicand and a three-digitmultiplier as provided for in the multiplicand and multiplier receivingdevices.

The buffer stage I4 is energized over a lead l5 from the units order RRUof the result register and the output of the buffer stage is transferredover a lead l6 to the tens order RRT to effect carry thereto after eachtenth pulse is applied to RRU. The buffer stage |4 provides a delay intransferring the pulse from RRU to RRT so that the carry pulse will notbe applied to RRT at the same time it receives its normal input pulse.When RRU produces an output pulse in response to each tenth input pulseit does not change the conductive condition of the buffer stage Mbecause that pulse is of the wrong polarity to effect such a change.However, the next negative E pulse transferred over line |2 to RRUcauses a positive pulse to be transferred over the lead |5 to the bufferstage from RRU and the buffer stage then transfers a negative carrypulse to RRT to advance it by a count of one.

The buffer stage I1 is energized over the lead |8 from the tens orderRRT of the result register and the output of the buffer stage istransferred over a lead |9 to the hundreds order RRH to effect carrythereto. The buffer stage functions in exactly the same manner as doesbuffer stage l4.

Carry between BBB. and RRTh, RRTh and RRTTh, and RRTTh and RRI-I'Ih isconveyed over the leads 26, 2!, and 22, respectively. No delay in theapplication of these carry pulses is necessary because the carry pulsesconstitute the sole input to these orders.

The multiplicand is entered into the result register a number of timesequal to the value of the multiplier, the multiplicand being entered inthe units, tens, and hundreds order of the result register inaccumulator fashion. This is to say that the units, tens, and hundredsorder respectively of the result register receive simultaneously anumber of pulses equal to the units, tens, and hundreds digital valuesof the multiplicand during a. single cycle of the multiplicand receivingdevice. The actual entry of the multiplicand to the result register iseffected by the gates 23, 24 and 25. Positive E pulses are transferredcontinuously from the line |0E to these gates over leads 26, 21, and 28,respectively. The output of the gate 23 is transferred to RRU over alead 29. The output of the gate 24 is transferred to RRT over lead l6and the output of gate 25 is transferred to RRH over lead I9. Themultiplicand receiving device controls the entry of pulses into theresult register by efiecting selective transfer of voltage over theleads 32, 33, and 34 to condition gates 23, 24 and 25, respectively, torespond to positive E pulses.

The gate 35, normally conditioned, is continuously supplied over a line31 with positive F pulses from line ltlF. These pulses render gate 35momentarily conductive and negative pulses are transferred over lead 38to the multiplicand receiving device Mc. However, these pulses have noeffect upon M0 unless it is not in its initial stable conditionwhereupon a single pulse switches it to its initial stable condition.The gate 36, normally de-conditioned, is continuously supplied over alead 40 with negative E pulses from the lead IBE. These pulses have noeffect on gate 36 until it is conditioned and then allow it to effectpulse transfer over leads 39 and 38 to the multiplicand receivingdevice. Whether pulses transferred from gate 36 will effect the stablecondition of the multiplicand receiving device depends upon the biasapplied to the device over a lead 4|.

The conditioning of gates 35 and 36 is controlled by the trigger Tmcwhich is normally in the Left condition. When the trigger Tmc isswitched to the Right conditiomgate 35 is deconditioned by the voltageapplied to it over lead 42. At the same time a voltage is applied over alead 4| to the multiplicand receiving device to render it responsive topulses from the gate 36 and a voltage is applied over lead 43 to thegate 36 to condition it.

After the multiplicand receiving device has completed its cycle ofoperation, a bias is applied over the lead 44 to the trigger Tmc whichpermits the trigger to be switched Left by the next negative F pulseapplied to it over lead IUF.

The multiplier interpreter 47, triggers 48 and 49, calculate switch 56,and gate 5| comprise all the remaining blocks shown in Fig. 1.

Calculate switch 53 is operated to condition the system for operationand thereupon a pulse is transferred over a lead 52 to switch trigger 49to the Right condition. At the same time a pulse is transferred overleads 52 and 53 to MpH to change the conductive condition of one of thedigit-representing elements thereof. When another one of thedigit-representing elements of MpH switches to one conductive condition,it causes a pulse to be transferred over leads 54 and 55 to the trigger49 to switch it to the Left condition. At the same time, a pulse istransferred over leads 54 and 56 to the trigger 48, to switch it to theLeft condition.

Trigger 49 is connected via a lead 5'! to the gate 5| so that, whentrigger 45 is switched to the Right condition gate 5| is conditioned andwhen trigger 43 is switched to the Left condition gate 5| isde-conditioned. After gat 5| is conditioned it is rendered conductive inresponse to the next positive D pulse appearing on the line HD andthereupon gate 5| transfers a negative pulse over a lead 53 to MpU.

When trigger 48 is switched to the Right condition, as describedhereinafter, a potential is transferred therefrom over a lead 59 tocondition the gate 46 thereby rendering it responsive to positive 0pulses from the circuit network The multiplier interpreter includes thecircuits 6!), 6|, 62, and 63. The conductive condition of these circuitsis dependent upon the condition of the multiplier receiving device Mpwhich is supplied with input entry pulses transferred over the lead 58from the gate 5|. As the last or lowest digit-representing element ofMpU has been sequentially cycled a pulse is transferred over a lead 64to MpT and over the leads 64 and 65 to one digit-representing element ofMpU. Similarly a pulse is transferred from MpT over a lead 66 to MpH andover the leads 66 and 6'Ito one digit-representing element of Mp'l.

Each of the circuits of the multiplier interpreter 4'! includes agrid-controlled tube. The circuits are inter-connected so that, when thetubes of circuits 60 and 62 are conductive, the tubes of buffer circuits6| and 63 are non-conductive. Also, when the tubes of circuits 60 and 62are non-conductive, the tubes of buffer circuits 6| and 63 areconductive. The latter is the normal condition of the circuits. Acontrol electrode of the tube of circuit 62 is connected through a lead63 to one side of digit representing push-button switches (Fig. 30)associated formly conductive to place the trigger in th Left condition.

While it has been explained that the trigger is switched from eitherstable condition to the other by the application of pulses to theterminal I, and hence to the grids of the tubes-L and R simultaneously,it is understood that the trigger may be switched from one stablecondition to the other by the application of a pulse to the control gridof only one tube or by any other conventional means such as plate orcathode keying.

In the schematic showing of Fig. 2a the trigger is designated as T as inFig. 2. The terminals shown in Fig. 2a correspond to thesimilarlydesignated terminals shown in Fig. 2. It should be noted thatthe absence of a connection to the terminal I in a schematic showingsuch as Fig. 2a indicates that capacitors 85 and 86 shown in Fi 2 areomitted. A connection to the terminal I indicates that the trigger isswitched from either stable condition to the other by the simultaneousapplication of pulses to the control grids of the tubes L and R. Aconnection to terminals C, P, bR, bL, gR, pL, PrL, gL, R, and prR.indicates connection is made to the cathode of the tube '1, the plateresistors 13 and 15, grid-bias resistors 18 of tube R, grid-biasresistor 82 of tube L, control grid of tube R, the plate of tube L, theplate resistor of tube L, the grid of tube L, the plate of tube R, andthe plate resistor of tube R, respectively.

PULSE SOURCES The following description is best understood by arrangingthe drawings as illustrated by Fig. 3.

The oscillator [0 (Fig. 3b) includes dual type tube 90 having two triodesections referred to hereinafter as 90L and 90R. The common cathode oftubes ML and 90R are connected to ground line 129 and the plates areconnected through their respective resistors 92 to the highvoltage line1471.. The control grid of each tube is connected through a biasresistor 93 to line 12g and the grid of each tube is connected to theplate of the other through a capacitor 94. It is seen that these tubesare connected as a conventional multivibrator. Such a multivibrator iswell known in the art and it suffices to state that the tubes 90L and99R are alternately conductive and non-conductive and vice versa becauseof small differences in the characteristics of those tubes and thecomponents used. This operation is continuous and causes positive andnegative pulses to be produced at the plates of the tubes 96L and 99R.When the voltage at the plate of BBL-is low the voltage at the plate of99R is high and vice versa. Hence, the voltage pulses at these platesare alternately positive and negative and 180 out of phase.

The plate of the tube 99L is connected through a capacitor 95 to thecontrol grid of amplifier tube 95E. The cathode of 96E is connecteddirectly to line 12g and its plate connected through a resistor 91 tothe line Mb. The control grid of tube 96E is connected through a biasresistor 98 to the line 12g. This amplifier may be of any suitableconventional design and serves only to amplify the pulses appearing atthe plate of tube ML. The pulses appearing at the plate of amplifiertube 96E are referred to herein as E pulses and are transferred over theline l DE.

A similar amplifier tube 96F is provided to amplify the voltage pulsesappearing at the plate of the tube 90R. These pulses are transferredfrom the plate of tube 96F over line HJF to the circuit network II andto other circuits referred to hereinafter. The circuit network II has 4triggers designated Tl, T2, T4, and T8 connected in series chain tooperate in binary fashion.

When in the starting or initial condition, each of the triggers Tl, T2,T4, and T9 is connected to be in the Left condition. Positive andnegative F pulses are applied from the line [0F to the terminal I oftrigger Tl. However, trigger Tl, as the remaining triggers, isresponsive only to negative F pulses so that positive F pulses have noeffect on the stable condition of the circuit. Terminal mL in the plateresistor of the left tube of trigger TI is connected over a line 99 tothe terminal I of trigger T2 so that when trigger T! is switched to theLeft condition a negative pulse is transferred over lead 99 to thecontrol grids of both tubes of the trigger T2 to effect a change in thestable condition of the trigger T2. In a like manner, trigger T2 isconnected to trigger T4 and trigger T4 is connected to trigger T8. Theoperation of these triggers may be understood by reference to Table Ibelow.

Table I CIRCUIT NETW ORK l1 Triggers Input Pulse (-F) T1 T2 T4 T8 L L LL R L L L L R L L R R L L L L R L R L R L L R R L R R R L L L L R R L LR L R L R R R L R L L R R R L R R L R R R R R R R L L L L It is seenthat the first input pulse (-F) applied to the terminal I of the triggerTl causes that trigger to switch to the Right condition. As a result, apositive pulse is transferred over the line 99 to trigger T2 but doesnot effect the stable condition of T2 because, as stated, it isnon-responsive to positive pulses. The second input pulse switches thetrigger TI to the Left condition and causes a negative pulse to beapplied over the lead 99 to the trigger T2 to switch it to the Rightcondition. Similarly, the third input pulse switches the trigger TI tothe Right condition. The fourth input pulse switches trigger TI to theLeft condition which causes the trigger T2 to switch to the Leftcondition which causes the trigger T4 to switch to the Right condition.Normal binary operation is continued through the sixteenth input pulse.The sixteenth pulsecompletes a cycle of operation and leaves alltriggers in the Left condition so that it corresponds to the zero orinitial starting condition. Subsequent input pulses cause a repetitionof this cycle of operation.

It is seen from Table I that the eighth input pulse causes the triggerT8 to switch to the Right condition. This switching causes a positivepulse to appear at the terminal pL and a negative pulse to appear at theterminal prR. Terminal pL is connected through lead I ID and capacitor109 to the suppressor grid of a tube G5I of gate 5| (Fig. 3a). Asstated, the pulses transferred over this

